Are your complex memory networks being designed without full knowledge of what’s going on inside of those large BGAs?
Do you know what’s going on inside of your BGA devices, but do not have sufficient functionality in your ECAD software to address advance timing skews?
The latest controller techniques for DDR3 include read and write leveling. The most basic of these features allows the controller to compensate automatically for the use of flyby topology in DDR3, which naturally skews signal arrival times at receivers. An extension of this technique within read leveling permits skew between individual bus bits to be compensated for within the memory system hardware itself. And there’s more.
As an applications engineer for Zuken’s PCB design suites – namely the CR-5000 Lightning and CADSTAR P.R.Editor HS applications – I know that having the best set of constraints to support these memory networks doesn’t matter if you’re still missing the data to support what can’t be seen.
Clearly, the end result of any high-speed memory network is for it to work properly when it’s charged-up. With the ability to front-end load constraints and create skew groups along with the schematic, the circuit engineer expects the perfect eye diagram and hopes for perfect alignment of signals across the entire bus in both the simulation results, and even on the bench test prototype.
Many designers follow the constraints supplied by the circuit engineer and painstakingly route the signals while referencing the base signals of their individual clock signals and differential pairs. Once the PCB designer has completed their job in routing these signals, a design review or a request for a re-spin of the PCB typically includes comments such as:
“I followed the engineer’s constraints and the report verifies my work,” or “…but I constrained the design per the chipset spec. The notes must be wrong!”
Regardless of the comments made, hundreds of route lengthening tweaks, moves and reroutes to compensate for timing errors must be made. Designing without full knowledge of the BGA’s internal features is like designing high-speed memory networks in the dark.
What’s really needed is knowledge of what’s going on inside the BGA packages. We know that chips are die packages. Each die pin is internally connected to its BGA package ball pad with a free space wire called a bond wire. These bond wires are not all the same length within the package.
In some well-known parts from Intel there may be as much as .790 mil (20.07mm) difference in skew between the shortest bond wire to the longest bond wire in the I/O for a CPU chip’s bus. The DDR2/3 chips will no doubt have similar bond wire skew differences; which compounds the problem of uneven timing results.
Locating the switch
The solution is to read the specification in its entirety. If your DDR 2/3 devices do not provide this information then you need to stop, contact the vendor, and request the information. This detail is often readily available in many data book specifications, or better yet, in a .CSV file provided by the vendor. When shopping for CPU and memory devices, consider a table of internal bond wire lengths as important as the reliability factor of the device. Without them your design will not work properly.
With this data in hand, it should be easy to input the individual pin lengths during the schematic capture phase of your design. Once this information is included in the PCB design it should be automatically referenced by the PCB ECAD routing tools, as in the case of CR-5000 Lightning and CADSTAR P.R. Editor HS.
Can you tell which design is more likely to work correctly?
Design A is more likely to work correctly since it contains the proper vendor specifications for the bond wire lengths.
Not having all of the information about your high speed memory devices, such as bond wire lengths, is much like designing in the dark. You may well find that reading the entire specification is like turning a light on, giving you the information you need for a successful design and saving yourself time on iterations.