Errors in collaboration are something that I’m focusing on quite a bit at the moment. Today I’m looking at the creation of topologies and error-prone collaboration between circuit designers and PCB designers when sharing constraints during the design process.
In most cases the circuit designer envisions a topology and communicates it by:
- Using freely placed text on the schematic
- Using handwritten notes and emails
- Overseeing the hand routing of clock signals and other critical nets
- Verifying constraints in spreadsheets not integrated into the PCB design
Now I know it’s not the lack of ambition or interest to improve the process, but more a lack of functionality with most EDA tools. Microsoft Excel® is not an EDA verification tool so why use it for that? Managing constraints within the circuit database is preferred. CADSTAR users have this functionality.
Constraints and Creating Topologies
Let’s consider one aspect of constraints: establishing a proper pin connection order and branch paths. This is known by many circuit designers as a topology; whether it is a basic daisy chain topology, or a complicated H-tree topology using remote branch points that must be balanced by length or delay between junction points…and don’t forget to consider the manufacturer’s required maximum stub length. However you look at it, the problem remains the same: the circuit designer must explain it and the PCB designer must create it, both with minimal communication.
Maybe you’re sick and tired of working this way? You’ll be glad to hear that we’ve got it sorted. This is where I do a little dance, take off my hat and say “Introducing…The New Constraint Browser and Topology Editor.”
What we’ve done for high-speed topologies is introduce a new module for CADSTAR that allows you to create these graphically using pin symbols, components and transmission lines.
With five predefined templates to choose from, any topology can be created including H-tree and user-defined topologies that incorporate virtual branch points. Topologies also support the control over stub length so no more painstaking entry of pin orders and branches using text-based attributes.Imagine if you had a solution like this during your repeated design review discussions on how your high-speed nets needed to be routed. Wouldn’t this have been easier? Using a graphical topology editor during the circuit design phase will trim hours off of the PCB Design process, simply by improving communications electronically.
Check out this video to find out more