It’s no secret that placing passive devices in the proper location, whether it is nearer to the source/driver or the receiver/load pins, makes the difference between poor signal integrity and optimal signal integrity. Often this can be impacted by a breakdown in communications between circuit designers and PCB designers. Typically, the circuit designer has the [...]
Errors in collaboration are something that I’m focusing on quite a bit at the moment. Today I’m looking at the creation of topologies and error-prone collaboration between circuit designers and PCB designers when sharing constraints during the design process. In most cases the circuit designer envisions a topology and communicates it by: Using freely placed [...]
Are your complex memory networks being designed without full knowledge of what’s going on inside of those large BGAs? Do you know what’s going on inside of your BGA devices, but do not have sufficient functionality in your ECAD software to address advance timing skews? The latest controller techniques for DDR3 include read and write [...]
Did you know you can save fan-outs and escape patterns and reuse them over and over again?
- For the entire design too – so this means that your next design shouldn’t take as long.
Fanning out high pin-count BGAs can be a simple one click operation, and creating escape patterns from the fan-outs can be done automatically as well.
