This is the second half of a series of blog posts that looks at the design challenges surrounding complex system-on-chips (SoCs) and through-silicon vias (TSVs), and how you can overcome many difficulties by using a 3D co-design environment. In the first post, I focused on why a co-design environment is needed and the importance of […]
In this two part series of blog posts I’m going to talk about the design challenges of complex system-on-chips (SoCs) and through-silicon vias (TSVs), and how you can overcome many difficulties by using a 3D co-design environment. Today I will focus on why a co-design environment is needed and the importance of optimizing interconnect. The […]
In my time working with companies in the automotive, telecom/wireless and defense industries, I often hear of the many issues facing design teams as they tackle projects made-up of multiple PCBs connected by flexible PCBs, cables, or with a backplane board. Often, the challenge arises when defining and implementing the interconnects across boards, and managing […]
Once in while you come across a feature or application that you find a new use for when you least expect it. Recently, I was working on a project with an electronic design group and we decided to start the 3D modeling of the complete assembly to start some joint analysis with the mechanical engineering […]
I recently gave a presentation on Power Integrity analysis at PCB West. The presentation, available below, looks at the increasing challenges with power distribution systems on modern high-speed PCBs and considers: IC input impedance behavior, resonance behavior of power distribution systems (PDS), management of decoupling capacitors and EDA methodology for concurrent power integrity simulation throughout PCB design process.