Are your complex memory networks being designed without full knowledge of what’s going on inside of those large BGAs? Do you know what’s going on inside of your BGA devices, but do not have sufficient functionality in your ECAD software to address advance timing skews? The latest controller techniques for DDR3 include read and write [...]
Recently, a discussion flared up in our office after someone questioned the use of the term ‘trunk routing’. They wondered whether it’s really a term in its own right – or just a fancy name for bus routing? The question was raised by someone who’s not that familiar with our high-speed design tools – so [...]
The importance and recognition of Signal Integrity (SI), Power Integrity (PI) and Electromagnetic Compatibility (EMC) in PCB design continues to grow. Just a few weeks ago I had one busy week participating in various seminars on signal integrity and EMI simulation. The first saw me flying to Oslo in Norway for the DNU Spring [...]
In the first part I covered just the bare essentials of why Low Voltage Differential Signalling (LVDS) is so popular. So what’s important about how these high-speed differential signals are routed, and why? I’m going to focus here mainly on PCI Express, but the differential routing considerations apply equally to other LVDS technologies and to differential [...]
Introduction Over the next few weeks I’m going to talk to you about the high-speed design challenges associated with Low Voltage Differential Signalling (LVDS) and how to overcome them. Today I’ll start by mentioning some applications of LVDS and some basics about how it works. Next week I’ll share my knowledge on effective and efficient [...]
In most cases, constraints are usually controlled by Electrical Engineers, and they drive the rules and requirements for critical nets from their schematic capture package. This is usually the most effective way of managing constraints, as it allows an organization to assign a point of control for maintaining the integrity and intention of a design concept. The down side of this approach is that if any design changes occur, or if critical nets do not meet routing requirements, there can be a significant increase in the potential for board defects. But there is another way – having the flexibility to utilize a Constraint Management tool to pass constraints at ANY point within the design phase, and to report and track changes made.
Recently, I attended the HSPICE SIG (Special Interest Group) event held in Santa Clara as an adjunct to DesignCon 2011. Zuken was invited to host a booth as an HSPICE Integrator Program partner. I thought I’d take this opportunity to share with you the highlights of the day. More About Synopsys HPSICE SIG The Synopsys HSPICE SIG is [...]
So you’re facing shorter design cycle times due to rapidly emerging global competition and the pressure to meet quality control standards, among many other things like drastically changing technologies that deal with faster speeds and sophisticated IC packages; introducing complexity to the simplest of design flows. Today what I’m going to talk to you about [...]
Some of you already suggested the correct answer (was it the coffee mug prize which attracted you to actively participate?) This New Year quiz did not require too much effort, did it? Click here to see the first post. Thinking about the IC on the lower part (D200) – as it is a high-pin count [...]
First of all Happy New Year, I hope you all had a nice holiday period. Here comes the second ‘Spot the Mistake’ brainteaser. If you didn’t catch the first ‘Spot the Design Mistake’, why not go and check it out now. This is an excerpt from a design where we supported a company with some design optimization consulting [...]
