Complete 3D Co-design System

A Case for a Complete System in a 3D Co-design Environment Part 1

In this two part series of blog posts I’m going to talk about the design challenges of complex system-on-chips (SoCs) and through-silicon vias (TSVs), and how you can overcome many difficulties by using a 3D co-design environment.

Today I will focus on why a co-design environment is needed and the importance of optimizing interconnect.

The need for a hierarchical SoC, system-in-package (SiP), and board co-design in 3D

As ICs are stacked, packaged and placed on PCBs, there are new system optimization challenges that require a new type of design environment enabling hierarchical SoC, system-in-package (SiP), and board co-design in 3D. For designers to create complex SoCs within a SiP using through silicon vias (TSVs) effectively, standards and integration specifications need to be defined; and organizations such as Si2 and GSA are working closely with the industry to do this. The problem is SoCs and advanced packages, such as SiP or package-on-package (PoP), and the board layout are typically designed in separate environments. Information can be communicated and exchanged from SoCs across different toolsets using file formats such as OpenAccess and LEF/DEF. But due to these new challenges, design teams are finding it hard to consider the complete system when they make critical decisions at each design stage.

When a design reaches the package development stage, there are typically only minor modifications made to the IC’s floorplan or die bump location. And if changes are required, they are usually made during package design since there is generally a large amount of flexibility in the connectivity between the chip and the package.

Optimizing interconnect

With high-speed differential signals propagating from the die to the package, and the package itself being designed with many power and ground supplies, the strategic definition of power and ground solder bump locations need to be considered. Factors include:

  • Parasitic cross-talk effects,
  • Signal quality,
  • Effective power distribution networks (PDNs).

These constraints have limited the freedom to optimize the connectivity between ICs and the package.

Does this sound familiar? If, so, then be sure to read the next blog post on this topic coming out next week for more information on how a co-design environment could really benefit you.


Written by

Humair Mandavia is the chief strategy officer at Zuken, responsible for the SOZO Center, Zuken’s US R&D division in Silicon Valley. His responsibilities include working with industry-leading companies in the automotive, IoT, and other key technology sectors to help drive the latest innovations in electronic design to the market. A member of the Zuken team since 2004, his past roles include solutions architect, product manager, and director of engineering. Professional experience includes working as hardware design engineer at ADC Telecommunications designing ATM and SONET applications. Mandavia received his bachelor of science in electrical engineering and his MBA from the University of Texas at Dallas, and is a current board member for Si2.

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