Advanced Chip Package Board Codesign

Advanced Chip-Package-Board Co-design

Chip Scale Review: Advanced Chip-Packaging-Board Co-designNote: The following article appeared in the July-August 2018 edition of Chip Scale Review

The proliferation of packaging designs that combine multiple chips into a single package is creating new challenges for package, printed circuit board (PCB) and integrated circuits (IC) designers. The common practice of designing the package, PCB and IC in standalone environments requires time-consuming manual processes that are error-prone and limit the potential for design reuse. What is needed are 3D co-design tools that integrate planning and final design implementation at the system level for PCBs, ICs, packages and mechanical enclosures.

The ability to conduct system-level co-design makes it possible to optimize bump and ball placement, I/O placement and pin assignment to lower chip, package and PCB layer counts even in nontraditional structures with routing complexity in both vertical directions. The emerging IEEE 2401 design file format standard goes one step further by offering the potential to streamline the process of communicating design data with customers and partners using different electronic design automation (EDA) tools or with third-party software.

Written by

Tom Whipple is a Solutions Architect in the Zuken SOZO Center. He has been with Zuken since January 2017. He previously worked for Cadence and VLSI Technology. He has Master of Science and Bachelor of Science degrees in Electrical and Computer Engineering from University of Arizona and Brigham Young University respectively.

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