What does it take to develop a successful new product in today’s highly competitive global electronics marketplace? It all starts with a systems architect tasked with seamlessly moving between the many different disciplines – functional block diagramming, floor planning, space planning, cost estimating, etc. required to define the hardware architecture. This special guy or gal then must work the magic needed to define a hardware architecture that meets all of the targets – functionality, cost, weight, style, battery life, etc. – required to ensure that success of the product.
In my previous post in this series about effectively reusing design modules to increase product quality and decease development time, I challenged you to think about how well you’re making use of existing design modules and why getting better at this could be a competitive differentiator. I looked at some of the design challenges circuit designers are facing, such as miniaturization, proliferation of electrical constraints and high speed design requirements, as well as some of the potholes it’s easy to fall into when working with modular design.
Although we’ve been talking about it for years, in PCB design it has yet to catch on in quite the same way despite there being a host of benefits to be reaped from modular design practices. So in the first of this two-part series I’d like to challenge you to ask yourself a few questions about how you reuse designs.
You’ll already be well aware that EMC compliance is a necessary condition for releasing products to market. There’s National and International bodies such as the IEC and the FCC that define limits on how much a device is allowed to produce, and the how stringent these are will vary according to industry.
A new generation of 3D multi-board product-level design tools manages multi-board placement in both 2D and 3D and enables co-design of the chip, package and board in a single environment. Multi-board design makes it possible to create and validate a design with any combination of system-on-chips (SoC), packages and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment, and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.