Custom attribute lists for design and panel data can be configured and saved using CR-8000 Board List Processor. Each list type includes many attributes that can be selected to output. The list can be used for in-house purposes or vendor requests.
Sometimes, engineering requirements force designers to swap the position of conductive layers in a board stackup. With CR-8000 Design Force, you can do this simply and quickly by using the Restriction/Block functions.
In CR-8000 Design Force, the Generate Bump utility allows the designer to add a bump line either single or sequentially to a differential pair route. Bump line size, style and space can be set in the dialog. Accurate length differences can be seen in the Constraint Browser during this process.
Ghosting of the template areas can be seen when dragging the cursor over its outline regardless of the visibility of the template layers. This will happen when the template layers are set as “Selectable layer” in the Layer Settings dialog. This is most common so the designer can select templates regardless of the active layer.
Design Force 2017 has improved the offset via function by adding efficiency in pulling out tracks from vias, creating BGA designs and build-up designs. The controls are based on the following: Qualified padstacks, rule-based layer pair vias, and parameters specified in teh offset via command panel.