Laying out high-speed buses has become a truly joined-up science, with both PCB and IC designers on the team.
You can tell when something isn’t as clear as it should be. The same questions come up time and again. You ask three experts and get three different answers. Routing differential pairs can be like that. Why? Because “it depends” – on exactly what signals those pairs are carrying and what kind of PCB you’re creating.
Luckily, where signals need return vias, component vendors often do most of the work for you. Let’s look at a PCI Express differential pair. First, the standard connector, showing its pinout but not its body; I’ll cover the connector body in a moment. The signal pin assignments are also standardized.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.