Author: Tom Whipple

Advanced Chip Package Board Codesign

Advanced Chip-Package-Board Co-design

The proliferation of packaging designs that combine multiple chips into a single package is creating new challenges for package, printed circuit board (PCB) and integrated circuits (IC) designers. The common practice of designing the package, PCB and IC in st and- alone environment s requires time – consuming manual processes that are error-prone and limit the potential for design reuse. What is needed are 3D co-design tools that integrate planning and final design implementation at the system level for PCBs, ICs, packages and mechanical enclosures.

Advanced Packaging with CR-8000's Design Force

Advanced Packaging with Zuken’s CR-8000 Design Force

Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs. It seems surprising that there are so few reliable EDA solutions out there, but CR-8000 Design Force is definitely the tool to look to when tackling advanced package design! Take a look below and see why.

Toshiba Embedded Module

Toshiba – RF Module Shrink (TransferJet™)

Toshiba faced a difficult design problem: their TransferJet™ technology was embedded in a customer cell phone, and when the next rev of the phone came around, they learned that they needed to shrink the board from 8mm x 8mm to 4.5mm x 6mm, and they had to shrink the module thickness from 1.7mm to 1.0mm. The original design was a simple board with a wire bond package and several peripherals. Competitive pressures required a significant reduction in size and thickness.