DesignCon 2017

DesignCon 2017: What’s Hot on the Electronics and Engineering Agenda

Mr. ChiphedA few weeks ago I was at DesignCon 2017, with the other 3999 people that registered for this annual event; learning about the latest hot topics being talked about in the industry, which included modelling and analysis of high-speed digital circuitry, the latest fast memory architectures such as GDDR5, DDR5 and DDR6, power distribution and power integrity, plus wider engineering issues such as IoT and eLearning.

I spent my time dipping in and out of the 14 themed conference tracks (with more than 100 sessions), looking around the 185 exhibitors, and couldn’t miss the chance to meet the conference mascot, Mr. Chiphead for a selfie. I also participated at the Synopsys HSPICE SIG on Thursday where Zuken had a partner booth and on Friday I attend the IBIS Summit where more than 60 industry experts met to discuss future IC modelling and standardization issues.

Technology topic highlights

So what were the highlights of the show for me? I can only share a few, as otherwise this summary would span over 10 blog posts rather than just one, but worth a mention are:

  • Many presentations had an emphasis on modelling and analysis of high-speed digital circuitry. Engineers these days are desperate to preserve the signal integrity of the todays GBits-per-second data stream. Communication speeds have reached 56GB/s as a commodity for lots of application these days. This implies new communication and data encoding schemes like PAM4, where we leave the good old days of a simple digital 0 and 1 coding while encoding the information within a ‘data bit’ into multiple levels, multiplying the possible bandwidth. So it looks like the world of electronics is going analog again (upon reflection was it ever really digital at all?) There are further advanced technologies to be expected in future (e.g. for 400 GB/s Ethernet the experts talk about things like PAM8).
  • All these cool systems are of course even more sensitive about noise issues, that require advanced design on the board level and need dedicated analysis technologies involving specific modelling techniques like IBIS-AMI. The IBIS-AMI standard celebrates its 10th birthday this year and was another hot-topic for many presentations and panel discussions. These so called “algorithmic IC models” do allow you to model things like pre-emphasis, various equalization schemes and jitter issues of advanced SERDES channels. (BTW: In CR-8000 we have implemented SERDES simulation and IBIS-AMI support in revision DF2016.000 exactly for these reasons).
  • New fast memory techniques show up at the horizon. Experts from NVIDIA and Micron introduced memory architectures like GDDR5, DDR5 and DDR6, projecting datarates of 8-16 GBs for these memories, new clocking schemes (‘mesosynchronous DRAMS’) and advanced technologies like equalization to be used in this domain as well.
  • This year again there have been a significant number of tutorials and panel discussions devoted to power distribution and power integrity — among the most challenging technologies for ensuring todays signal integrity. Focused presentations covered power delivery networks, bypass capacitors (their role in suppressing noise and jitter), distributed low-dropout regulators (LDOs) and power delivery for chip, packages and boards. These sessions reviewed the state of the art and did identify the technology challenges moving forward implementing tomorrow’s 10- and 7-nm chips onto the boards.

DesignCon’s technical sessions not only focused on knotty engineering problems such as overcoming chip and module package parasitic’s, material losses and reflections, high-speed serial clocking, techniques for measuring and simulating noise effects, advanced test and measurement methodologies and the analysis of system interconnects. They also addressed general issues like IoT and its impact on automotive and smart cities in future plus eLeaning…just to name a few. The opening day keynote by Dr. Zoltan Cendes, the founder of Ansoft Corp. — “Turning Signal Integrity Simulation Inside Out” — set the focus point for the entire conference.

Till next time Santa Clara – Ralf.

Written by

Ralf works as Product Manager for High-speed Design Systems at the Zuken EMC Technology Center in Paderborn/Germany, responsible for product marketing and business development for the Zuken SI, PI and EMC analysis tools. He holds a diploma degree in computer science, electrical engineering and economics from the University of Paderborn. He has 30 years of experience in Electronics and EDA. He is regular speaker on international conferences, but is involved in European Funding project and standardization activities as well.

You may also like...