Getting Signal Integrity Right by Design
Modern PCB designs have IOs reaching speeds of multi Gigabits per second, making signal integrity analysis an imperative for any product in the design phase. As the industry spends increasing amounts of time on finding and fixing these issues, it’s worthwhile any designers out there that are not already doing so, investing some energy in reducing design cycle time through early identification of high speed issues like crosstalk and return path discontinuity etc. Let me go into why it’s worth your effort…
Higher speed performance and lower power consumption
The ever increasing data rates, higher I/O counts and greater design complexity are leading to greater challenges in meeting SI and electromagnetic interference (EMI) requirements. For instance, 3DIC technology uses through-silicon vias (TSVs) to eliminate bond-wires and further reduce interconnection distance in stacked chip configurations. This provides higher speed performance and lower power consumption at the cost of creating many new instances for harmful radiation to arise.
The cost of late SI analysis
During the design phase, a lot of attention is typically paid to ensure that physical design rules are met. But on the other hand to judge electrical performance, simulations are usually performed after the design is relatively mature through extensive 3D solutions of Maxwell’s equation. The result, all too often, is that large numbers of SI problems are identified at a point relatively late in the design process when changes are very expensive to make. As a general rule, the cost of design changes generally increases by an order of magnitude or more as the design moves from conceptual, to detailed, to simulation phases.
How to do early design checks
So now you understand why, now you most likely want to know what is there out there to help you do this. If you’re already using CR-5000/CR-8000 or CADSTAR PCB designing software , you might have heard of the EMC Adviser tool that is integrated into the PCB design environments to offers a ready means of checking for these issues in the design phase, allowing the person doing the layout to identify critical pain points without having to wait for an answer from the simulation team (which can sometimes take a few days). For final verification, there are simulators integrated within our CR-8000 environment, which allows both the layout/design engineer or the simulation engineer to run transient or frequency domain analysis.
Common design mistakes
What if you had a trace routed close to the edge of a reference plane and it was a critical high speed net. You don’t have to wait for your simulation team to come back and tell you to fix it. Just run the check for it in EMC Adviser, which will detect this pretty quickly. And no need to break into a sweat on making sure you have ground vias distributed throughout your design. With just the click of a button within the EMC Adviser, the whole design will be checked to ensure that all layers have sufficient return vias with a user-defined density. The same can be said about issues like a missing ground shield which may drive up crosstalk, causing an interface to fail. These are just some of the more than 30 checks which can be performed.
If you’d like to find out more about EMC Adviser check out our website. I should also say thanks to The PCB Design Magazine who published a similar article from me on this topic in their July issue.