Design Rule Violations and PCI Express Design
Last week I was over in the beautiful city of Dresden, Germany; involved in Zuken’s participation at the FED conference – arguably the most significant PCB event in Germany during the year. Apart from our annual conferences in Ulm and Hannover of course ;-)Masoud Raeisi and I were very busy manning our own Zuken booth, supporting the booth of our German CADSTAR reseller CSK, working with Würth Electronic who we have recently started partnering with, and each presenting a session on the agenda. Let me share with you the highlights of what we were presenting…
The importance of solid return paths – Masoud Raeisi
The talk discussed a fundamental design rule violation PCB designers often make – to cross a gap/split in the reference plane underneath, not knowing the consequences:
- Signal timing
- Which can be affected by up to 18 ps on the investigated 1.5V DDR2-667 control line – what are your DDR2 skew requirements?
- Impact on the radiated emissions from the signal net (as shown).
PCI Express design and analysis challenges – Ralf Bruening
During this session I presented the design challenges of designing with a PCI-Express system.
- Did you know that there are more than 30 electrical design requirements identified by the PCI Express (PCIe) specification from the PCI-Express Special Interest Group (PCI-SIG)?
- Ensuring design robustness requires careful planning, and a thorough understanding of your design’s electrical behavior.
- PCI Express Differential Pair Spacing for Stripline/MIcrostrip and Length Matching Rules – select to enlargeMany of these most critical electrical performance requirements PCB designers have to comply with to ensure the proper operation of the PCI Express link, raising issues such as:
- Trace geometries, vias, and reference plane discontinuities
- Bit error rates (BER)
- Quality problems related to the interface link and used connectors
The presentation went on to cover the following topics:
- Stack-up and material requirements for a PCI-Express design
- Routing, spacing and skew/length difference requirements
- Eye Diagram Requirements for a PCI-Express channel and Simulation Result (RX Side) – select to enlargeThese include a maximum allowed skew of 5mil (the tiny distance of 0.127 mm which nets are allowed to differ in length)
- Verification issues with respect to how and where signal integrity simulation such as Zuken CR-5000 Lightning/CADSTAR SI Verify can help to predict the electrical performance of the PCI Express link
If you would like more information on each of these presentations please drop me an email or comment on this post and I’ll gladly get back to you.
Somehow in between all that I managed to see a bit of the city, the amazing old baroque ‘Elbe Florence’ and the valley of Elbe.
Oh and I almost forgot the EDA vendors roundtable, where we presented our new innovations in electronic design – CR-8000 Design Force. Subsequently the interest kept Masoud very busy on the stand as he showed people around the software. Here’s a taster of CR-8000.
Next year’s conference is scheduled for the third week in September, in Bremen, North Germany. I plan to be there – will you be coming too?
Zuken Innovation World
I will be presenting on ‘CSI PCB – Who/What killed my PCB ?, ‘Bridge over Troubled Constraints – PCI-Express Design Mysteries’, amoung others at Zuken Innovation World events in Europe and North America.
Zuken Innovation World conferences are our premier annual events for the Zuken community. Held in locations around the globe, the conferences bring together our customers and industry professionals in an environment that encourages networking, learning, and sharing of innovative ideas.
See www.zuken.com/ZIW for more details and to find your local event.