Implementing FPGAs within PCBs through Intelligent Communication
Incorporating FPGAs into PCBs designs can be tricky and involves a constant dialog of communication between the FPGA designer and design and PCB/layout designer throughout the process – which can be tiresome, tedious and, worst of all, time-consuming.
Introduction to FPGAs
If we look inside the box of any electronic product around us, many would find a programmable device, such as a field programmable gate array (FPGA), implemented within the design. These programmable devices allow designers to control the functional behavior of that product easily. Such FPGA devices have changed the environment of electronic product design by giving the designers greater flexibility in providing a tailored solution for their customers. But all this comes at a price that is paid for during product development.
If there is one area of PCB design that will cause some stress, then it is sure to be when we include FPGAs on a PCB. The flexibility and functionality of the FPGA is excellent and offers significant benefits for the electronic product being designed. However, it does pose several challenges when it comes to the design of the PCB. During the design process, the PCB is usually designed in parallel to the FPGA. Throughout this concurrent engineering process there are many pin assignment changes. This leads to multiple iterations of FPGA pin assignment, either driven from the FPGA implementation or the PCB design.
Typical Design Process and Communication Flow
1) Device selection and initial pin assignment
- Selection of the device by FPGA engineers
- Followed by communicating this to:
- A librarian for the part to be created
- The design engineer who captures the design intent, including the FPGA
- Hardware engineer for first pass of the pin assignments
2) Floorplanning and layout by PCB designer
Once the initial logical circuit design is captured, floorplanning and layout can proceed.
3) If/when the layout engineer finds a problem in routing the design, pins may need to be swapped to improve the routability. The complexity of these devices (which is also one of the benefits), makes it harder for the layout designer to know if pins can be swapped. There are many factors to consider, for example:
- Technology of the signal/pin (SSTL, HSTL, LVCMOS, etc)
- Functional specification of the pin (differential pair, clock pin, etc)
This may be a manual task, working with hardware or FPGA engineers to request whether pin changes are legal and acceptable. A manual process would then follow to request the change throughout the data for:
4) These changes are passed to the FPGA designers, who in turn are working on design changes within the FPGA. Both of the changes now need to be incorporated together and checked for compatibility. The new configuration is then implemented within the FPGA environment and the resulting pin assignment can be sent back to the hardware and layout engineers.
As you can imagine, this may lead to several iterations of design changes; either as a result of manual information exchange errors, incompatible pin changes or new pin assignments.
Tiresome, tedious, and time-consuming are just some of the words that spring to mind in this process.
Taking Out the T’s and Replacing with Intelligent Communication
To make life easier, wouldn’t it be nice to communicate intelligently during the design process, so that layout engineers can make changes and continue the task without checking each change with the FPGA engineers?
It would also be great if we could generate the change information electronically, in a form that the FPGA could use more readily, and allow the layout engineer to receive design changes and updated pin assignments in an electronic form that can be imported into the PCB design process as an engineering change order (ECO).
Introducing the Graphical Pin Manager
So that’s exactly what we’ve done by developing CR-8000 Graphical Pin Manager (GPM). It means that:
- Librarians can create parts very quickly and efficiently utilizing the built-in device kits.
- FPGA engineers, design engineers and PCB layout designers can read and write the pin constraint/assignment information and perform pin swaps to optimize PCB design, work together and communicate pin assignment changes intelligently.
The improved design process enables and encourages a co-design environment for FPGA and PCB design. GPM also includes support for the CR-5000 suite of tools.
Improved design flow
FPGA Technology of the Future
My view is that this technology is going to expand in complexity, which in turn will help it to extend further across all markets for electronic products. Both Intel and ARM are working with FPGA vendors to provide added functionality to their already powerful devices. In future we will continue to see low power, signaling technology and methods, while continually extending the functional capability of these devices.
What do you think?