Improve your PCB Quality and Cost with Concurrent Power Integrity Analysis
I don’t always make it to all the tradeshows during the year, but I was lucky to attend PCB West in Santa Clara earlier this year where I had an opportunity to do a presentation on Power Integrity analysis that my colleague Ralf Bruening and I put together, and how it can save time and cost by doing this analysis concurrently with the board layout.
Along with the nice weather and great cuisine, the conference turn-out was amazing. It was good to see the variety of individuals and disciplines present at the conference. We had many visitors attend our booth, and most of the attendees were excited with our Blackberry Playbook giveaway.
Presentation now available
I received lots of requests for the presentation paper, so I’m happy to say it is now available via SlideShare – see below, or you can download it here from SlideShare.
In summary, the presentation looks at the increasing challenges with power distribution systems on modern high-speed PCBs and considers…
- IC input impedance behavior
- Resonance behavior of power distribution systems (PDS)
- Management of decoupling capacitors
- EDA methodology for concurrent power integrity simulation throughout PCB design process
Other PCB West highlights
As well as presenting our paper we were also supporting the IPC-2581 booth, which also received a great deal of attention – and eventually led to a great dialog during the panel discussion later that day on data transfer for manufacturing. You can refer to a previous post as to why we believe IPC-2581 is so important.
It was a busy PCB West 2011! We have already signed up for 2012, so perhaps we will see you in Santa Clara next year (September 25-27 2012)
In the meantime, if you have any comments or questions, please leave them below.