Reduce Thermal Analysis Time Early on in the Design Process with Chip-Package-Board Co-design

Thermal issues have long been one of the many Achilles heels in electronics design, in much the same way that electromagnetic noise and interference messes with your board. My blog post looks at how thermal dissipation is growing to be a much bigger beast than ever before as semiconductor companies and OSATs strive to better their products in the battle against time-to-market and better performance by stacking integrated circuits (ICs) in a package. Then I’ll be taking a look at how you can overcome thermal issues using new methodology through bringing the package, chip and board design environments together.

Wanting more and less is no oxymoron

I want more! More storage for my pictures, videos, music, emails. And yes I want less too, less load time. And I want to have my cake and eat it…all of this using less power. Sound familiar?

Stacked chips and wafer thinning increases thermal diffusion

The latest method of meeting this familiar more and less demand by consumers is by integrating semiconductors and stacking those chips on top of one another using through silicone vias (TSVs) on multiple substrate layers – also known as 3D ICs.

To achieve this, the wafer and TSV insulating film on the wafer needs to be thinned, which can cause greater thermal issues than on traditional boards. Just in the same way that thin walls in a building are going to lose heat more quickly than two-foot thick walls.

We’re always talking about the importance of looking at design challenges as early as possible in the design process, but this is even truer for the latest 3D stacked chips. Getting that early feedback has an even greater potential to save design time and money than in traditional or 2.5D integrated packages. The only way that is truly possible is through system-level co-design between the chip, package and the printed circuit board (PCB) design processes.

Rule-of-thumb assumptions are not good enough

When IC designers use rule-of-thumb-based assumptions for predicting thermal behavior using rough specs, there is no doubt that they risk higher costs, and more system malfunctions. This is simply because it is more difficult to predict the heat radiation on a stacked IC. To understand the real impact of heat radiation you need to consider:

  • The package that encapsulates the IC
  • The layout of the PCB and peripheral parts

Case study: CPU with multiple stacked chips on a four-layer substrate placed on a PCB

To show you how to improve thermal analysis for more functionality and better performance, I’m going to use a real life case study. In this case it was a newly designed CPU within a package for an automotive application, with a four-layer board using the DDR routing of existing package products and passive components. We used Zuken’s CR-8000 Design Force for this part of the process.

About the test board

  • The board data refers to the golden sample from JEITA LPB mutual design WG [2], which replaces the LSI section in 3D stacked IC. The substrate used is a four-layer 100mm × 80mm structure.
  • The CPU section is a 3D laminate structure that has been laminated using two sheets of memory die on top of the logic die (Fig. 2), with the logic die connected to the board via the resin interposer and BGA.
  • Logic die and a memory die are connected using fine solder ball shapes, known as microbumps and TSVs. In CR-8000 Design Force, we can build the 3D stacked IC described above with the resin interposer and moulding resin to view the complete system assembly. This allows us to visually check the 3D stacked IC system. The native 3D environment enables the option to output 3D mechanical data that includes the output of via and routing patterns as part of the STEP data with arbitrary precision.
  • Constraints were applied as part of the simulation run including a heat flow of 1W, which is given to the edge of CPU. The atmosphere from the portion exposed to the outside air (22 ℃) was radiation only.
  • The simulator utilizes the ANSYS mechanical engine to obtain the result of the steady state thermal distributions. For reference to the meshing and simulation times, the specifications of the hardware used are listed in Table 1.

Table 1. Hardware specs for simulation

OS Windows7 Professional 64bit
CPU Intel Core i7-4770     3.40GHz
RAM 16     B

Chip, package, board co-design in practice

There is a greater need for the system on chip (SoCs), PCBs and integrated circuits (ICs) design environments to work together to be able to holistically optimize the performance of each element of the design. Why? Because it saves time, improves performance and lowers manufacturing costs. Traditionally physically connecting chips, packages and boards doesn’t happen until further in the design process at the traditional analysis tool phase. But bringing them together at that point of development is painful and takes a long time. Then if you want to make changes to the design you’re manually communicating information back to the respective design teams. What we’re suggesting at Zuken is that there is another way: by integrating them together at the start using a method of system-level co-design to eliminate manual data exchange between chips, packages and board design environments, and perform trade-offs to improve the design at the start of the design process, you can overcome those exacerbated thermal diffusion problems.

System-level design for exploratory simulation early on

By creating a system-level view of the product within Zuken’s CR-8000 design environment, using data from package and chip design solutionsyou have the information to optimize routability via pin assignment and I/O placement so that you can get the maximum amount of layers between the chip, package and board.

Having this system-level data from the onset you can send this directly to the analysis tool, saving time in the import and construction (and modelling, meshing and simulating etc).

Co-design paradigms

By doing this you are talking about simulation taking hours, rather than days and weeks. But even this reduction wasn’t good enough; in this case example we wanted to push the limits and get it down to under an hour.

The ‘under an hour’ simulation target

We identified two specific areas that were causing the simulation to run longer, and worked to develop techniques to shorten this.

Problem source 1: The time it took for meshing and simulation when directly importing the CAD data using the STEP model, as a result of the high number of nodes in the data.

What we did: Replaced micro-bump ball shapes with octagon sides, then also treated the micro-bump array as one continuous sheet and characterized it with the conductivity calculated based on the conductivity of the underfill and solder.

Problem source 2: The high number of data nodes as a result of the board wiring patterns within the design.

What we did: Created a method using an algorithm to approximate the signal traces in a block shape rather than the actual routing shapes. The algorithm latticed regions based on the various resolution settings, and this preserved the conductive regions on the design, while also reducing the mesh count before simulation. And you know what? We didn’t compromise the accuracy of the thermal analysis because we retained the traces when we created the simplified model with the algorithm. By using this process we also reduced the STEP file size, making it easier to manage and exchange files between the CAD and CAE environments.

How fast?

By making these changes, we managed to speed up the analysis…

  • Meshing was completed in less than 1 minute for all 170,000 nodes.
  • For conducted heat transfer analysis, we got this completed in less than 1 minute.
  • We also managed to effectively study the temperature gradient of the internal ICs to estimate the heat dissipation during the conceptual design phase.
  • As we were able to consider the underfill material and the material for the moulded resin early in the design process, we were able to conduct accurate stress analysis with the heat transfer analysis.

It took a total of 56 minutes to be exact:

  • 30 minutes for the CPU section of the modified detailed board data
  • 10 minutes for STEP data output
  • 15 minutes to set-up in the simulator
  • 1 minute for analysis calculation

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Written by

Humair Mandavia is the chief strategy officer at Zuken, responsible for the SOZO Center, Zuken’s US R&D division in Silicon Valley. His responsibilities include working with industry-leading companies in the automotive, IoT, and other key technology sectors to help drive the latest innovations in electronic design to the market. A member of the Zuken team since 2004, his past roles include solutions architect, product manager, and director of engineering. Professional experience includes working as hardware design engineer at ADC Telecommunications designing ATM and SONET applications. Mandavia received his bachelor of science in electrical engineering and his MBA from the University of Texas at Dallas, and is a current board member for Si2.

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