As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.
It’s no secret that placing passive devices in the proper location, whether it is nearer to the source/driver or the receiver/load pins, makes the difference between poor signal integrity and optimal signal integrity. Often this can be impacted by a breakdown in communications between circuit designers and PCB designers.
In most cases, constraints are usually controlled by Electrical Engineers, and they drive the rules and requirements for critical nets from their schematic capture package. This is usually the most effective way of managing constraints, as it allows an organization to assign a point of control for maintaining the integrity and intention of a design concept. The down side of this approach is that if any design changes occur, or if critical nets do not meet routing requirements, there can be a significant increase in the potential for board defects. But there is another way – having the flexibility to utilize a Constraint Management tool to pass constraints at ANY point within the design phase, and to report and track changes made.
So you’re facing shorter design cycle times due to rapidly emerging global competition and the pressure to meet quality control standards, among many other things like drastically changing technologies that deal with faster speeds and sophisticated IC packages; introducing complexity to the simplest of design flows.