Tagged: Design Rule Checks

PCB Design Rule CheckingWhen it comes design rule checks for PCB designs, there are checks that should be performed that are just as important as spacing rules. Strict adherence to basic PCB design rule checks, such as track to track, track to via, via to via, pad to track etc. – though necessary to avoid short circuits – only scratch the surface when trying to identify potential design flaws.

Use Better DFM Checks to Improve Flex PCB Manufacturing Productivity

Use Better DFM Checks to Improve Flex PCB Manufacturing Productivity

Flex designs pose unique challenges for most PCB tools because traditional object checks don’t account for Flex checks nuances. They present a new set of objects that are best accounted for during the design phase. 

This forces designers to incorporate changes after the design data is off to manufacturing for build. The manufacturer must then perform the Flex-based checks on the design and relay the issues back to the designer. This leads to a frustrating loop that delays product releases and wastes money. 

The Importance of EMC Rule Checking

EMC = DRC²: The Importance of EMC Rule Checking

When it comes design rule checks for PCB designs, there are checks that should be performed that are just as important as spacing rules. Strict adherence to basic PCB design rule checks, such as track to track, track to via, via to via, pad to track etc. – though necessary to avoid short circuits – only scratch the surface when trying to identify potential design flaws. I often see PCB designs that are completed based on this premise and wonder what else could be hiding in the design?

Multi-board design

Getting Signal Integrity Right by Design

Modern PCB designs have IOs reaching speeds of multi Gigabits per second, making signal integrity analysis an imperative for any product in the design phase. As the industry spends increasing amounts of time on finding and fixing these issues, it’s worthwhile any designers out there that are not already doing so, investing some energy in reducing design cycle time through early identification of high speed issues like crosstalk and return path discontinuity etc.