Are you looking to increase the capabilities and complexity of your PCBs designed within CADSTAR? Maybe you’ve got pressure to deliver more functionality from others within the product development team, but are unsure how to deal with the resulting signal integrity and power integrity issues?
A few weeks ago, I had the pleasure of presenting a webinar concerning power integrity. It was a primer on power distribution systems and how to address the issue of getting enough charge to high frequency devices. This prompted me to write this blog post and share some of the ideas that you can implement immediately.
In the last few weeks I’ve been on the road visiting the well-attended Engineering Days in Benelux (Eindhoven), UK (Shropshire) and ZDAC in San Antonio, USA. My colleague Humair Mandavia and I formed a tag-team to introduce the new Power Integrity Advance solution to our customers; with my focus this time on our CADSTAR users.
I recently gave a presentation on Power Integrity analysis at PCB West. The presentation, available below, looks at the increasing challenges with power distribution systems on modern high-speed PCBs and considers: IC input impedance behavior, resonance behavior of power distribution systems (PDS), management of decoupling capacitors and EDA methodology for concurrent power integrity simulation throughout PCB design process.
Are you one of the many designers developing today’s complex PCBs? Those containing high pin count ICs like FPGAs or new microprocessors sharing multiple voltage rails? If you’re anything like the people I’ve been talking to recently, you might be suffering from time-consuming and costly problems in supplying the chips with power over the required frequency range. Yep – you’ve got a Power Integrity problem.