We’re happy to announce that Speedstack, Polar Instruments’ layer stackup design/documentation tools, can now be directly linked to Zuken’s CR-8000 Design Force and DFM Center.
Design Force can help you verify your design before you send it out to manufacture. Before running any signal integrity analysis in Design Force, you must assign device models to the pins in your components using the Constraint Browser.
I don’t think I’m generalizing when I say that designers working on complex high speed designs really don’t want to expend a lot of time and effort dealing with power integrity problems. And they especially don’t want to do it using tools that are detached from their design flow. In today’s complex PCBs, we’re talking advanced processors, complex FPGAs and superfast memories, which all share various voltage ranges.
Luckily, where signals need return vias, component vendors often do most of the work for you. Let’s look at a PCI Express differential pair. First, the standard connector, showing its pinout but not its body; I’ll cover the connector body in a moment. The signal pin assignments are also standardized.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.