Why Simulate PCBs at All? On-and off-piste Gigabit Signaling, Simulation and Modeling

This may seem a strange question for someone who’s made their living out of signal integrity for so long, but things have changed. There was a period in the 80s and 90s that I call the SI Deficit: the period when signal integrity issues took engineers by surprise and my specialty was even called “Black Magic”, as in the titles of well-known textbooks by Howard Johnson.

The design landscape has changed radically since then – the main reason for this being standardization. Double data rate memory, in all its forms, has been a powerful agent of change. Mass-production has meant that it is economic to use DDR2/DDR3 memory, whether or not its speed is required. Bus technology has undergone a similar process, with serialized, multi-gigabit-per-second differential data transfer in standards such as PCI Express and HyperTransport becoming the norm.

The risks of undetected signal integrity or EMC issues appearing in production hardware are too great to be addressed by simulation alone. Device vendors have introduced a swathe of counter-measures, designed to compensate for cheap, outsourced production and limited high-speed electronics skills.

You still need to simulate, but you need to combine it with as much structure, regularity and symmetry as possible in PCB design. By designing on-piste you are doing what the chip vendor and standards bodies expect: repeating the same assumptions they made and making performance predictable from the outset.

Once you’re off-piste, perhaps using a cost-reduced ground pattern in place of a full plane, going through an off-board connector or routing near a video signal, you need to simulate in greater detail and to know what you’re checking for.

On-chip countermeasures

Simplifying route topology

Current-mode drivers such as LVDS (Low Voltage Differential Signaling) are designed for point-to-point connections, since the signal voltage at the receiver is created by circulating a small current through the terminating resistor. Point-to-point routing creates fewer signal integrity issues since there are no signal reflections due to route branching and there is less scope for introducing other discontinuities.

Many high-speed differential channels are point to point. On-die terminations further simplify topology. There is less scope for unwanted glitches caused by complex routing geometry. Differential signaling is more resistant to noise than single-ended.

Single-ended route topology has not been overlooked either. In DDR3 memory, the address bus, which can connect to several devices, is routed as a daisy-chain. This topology is much simpler to route than the H-tree required to create equal timing in earlier memory buses. This has been made possible by extra on-chip intelligence to allow correct behavior when there is skew along address lines without any accompanying slowdown.

Matching of the two sides of a differential pair means more than just matching lengths. The entire pair must be routed as symmetrically as possible from the point of transmission to the point of reception. Some discontinuities partway along the routing cannot be fully compensated by hardware and need to be designed very carefully.

Discontinuities along the route length, including those in the third dimension, need to be minimized. Where a discontinuity is essential to the design, simulation is used to assess the impact. Select image to enlarge.

Signal conditioning

Signaling bitrates are now so high that, just like the Eurofighter, the signals won’t fly without intelligent controls. Pre-emphasis relies on transmitting a deliberately-distorted signal to compensate for effects that would otherwise reduce signal quality to an unacceptable level. If pre-emphasis is considered in the time domain, it means boosting the amplitude of low-high, high-low signal transitions; viewed in the frequency domain, it means boosting the high-frequency components.

Adapting to PCB characteristic impedance

Some FPGA devices now incorporate a start-up mode that allows the device to detect, and adapt to, variations in PCB characteristic impedance. Different impedance values create different ideal termination values and more

subtly, different ideal driver output characteristics to yield highest noise immunity. The technology is still developing in this area.

High-end and low-end devices

Sophisticated adaptive technology is presently confined to some high-end FPGA and other premium devices, so PCB design must also suit the weakest technology used on the board. PCBs still typically feature complex route topology with multi-drop/multipoint connects, external terminators and plenty of electrical discontinuities.

Black box versus internal structure models

IBIS gained popularity partly due to relative simplicity in creating models and partly because IBIS models, unlike their SPICE equivalents, reveal little about the device vendor’s precious IP.

An IBIS model (left) has only as many nodes as the external connections but an HSPICE model (right) usually includes many internal nodes, used inside the SPICE netlist to control buffer behavior

Models of passive components such as filters and connectors can be created by modeling the internal structure using a SPICE netlist or by entering the network directly as a circuit schematic. Such models are directly available from some vendors. Zuken has worked with selected vendors to provide downloadable obfuscated (hidden) models that hide the internal structure with no reduction of functionality.

Scattering Parameter (S-Parameter) models represent the “scattering” of sine waves of a single frequency from a device port on which it arrives to the other ports. I covered S-Parameters in an earlier blog, so I won’t go into too much detail here, except to mention the advantages and drawbacks of this kind of model. S-Parameter models are based on either hardware measurement or precise, detailed simulation, making no assumptions about internal structure. They are very accurate provided the scope of the input conditions is well-covered by the model; this normally requires hundreds or even thousands of entries. Measured results cover only the environmental conditions that were present when the model was derived, so noise and measurement error can be included by accident and the true operating environment can be different, invalidating the model.

In summary

Zuken’s CR series supports all the modeling methods I mentioned and some others besides. A rich range of modeling methods is essential in a world of dispersed design teams and flexible manufacture, which makes sure there’s always a way to go forward.

If you’d like to find out more, take a look below at a presentation I gave at the IEEE  recently called “Gigabit LVDS Signalling on a PCB Assisted by Simulation and S-Parameter Modelling”.

Or you can download it here.

Written by

Jane Berrie has been involved in EDA for PCB signal integrity since the 1980s. Her articles have appeared in many publications worldwide - too many times to mention. Jane is also a past session chair for 3D IC design at the annual Design Automation Conference. Jane’s also an innovator with a unique perspective, who constantly works on new solutions in the fast-evolving world of electronic design. In her spare time, Jane has organized themed charity events - including two in aid of lifeboats and red squirrel survival. Jane is also a regular disco-goer.

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